(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming Shallow Trench Isolation regions for the era of sub-micron semiconductor device feature size.
(2) Description of the Prior Art
In fabricating semiconductor Integrated Circuits (IC's), the areas in the surface of the substrate that are dedicated to the formation of separate device features must be electrically isolated from each other. A combination of device features form the finished device that has been designed and fabricated to perform a particular function and as such is referred to as an active device. The requirement of electrical isolation has given rise to a range of methods that are aimed at creating electrical isolation between device features and between devices within a semiconductor die.
The continuing trend in the semiconductor industry is to form semiconductor devices on silicon substrates that have increasingly higher device densities and smaller device feature sizes. This continued device shrinkage and increased device density brings with it new problems. One such problem in particular relates to the necessity of providing an efficient and reliable process to separate active devices that function on the current miniaturized scale. For the Very Large Scale Integration (VLSI) and Ultra Large-Scale Integration (ULSI) technologies, minimum device feature size of 0.25 um. is being approached. In the fabrication of such integrated circuits one of the most frequently used methods by which one region of the semiconductor substrate is electrically isolated from another region is the Shallow Trench Isolation (STI).
One other method that has previously been used to create isolation regions is the so-called "Local Oxidation of Silicon" (LOCOS) process. The LOCOS process is frequently used to form CMOS gate structures. For this LOCOS process, a temporary patterned nitride layer is used as a protection or resistant area to cover the future active areas during the subsequent field oxidation process. The LOCOS process can further briefly be described as follows: a pad oxide is formed on the surface of a silicon substrate, a layer of silicon nitride (Si.sub.3 N.sub.4) is deposited over the layer of pad oxide. The pad oxide is a thin thermal oxide that allows better adhesion between the nitride and silicon and acts as a stress relaxation layer during field oxidation. The nitride and oxide layers are patterned and etched thereby creating openings exposing those portions of the silicon substrate where the local oxidation is to be formed. A boron channel-stop layer is ion implanted into the isolation regions (of the CMOS device). The field oxide is grown within the openings and the nitride and the pad oxide layers are removed. This completes the local oxidation. A disadvantage of the LOCOS process is that the process requires long oxidation times (thermal budget) and that lateral oxidation under the barrier mask ("bird's beak encroachment") limits the minimum spacing between adjacent active device areas to about the 1 um range. This prevents further increases in device packaging density using the LOCOS process.
One method of circumventing the LOCOS limitations and to further reduce the field oxide (FOX) minimum feature size is to use shallow trench isolation (STI).
In using the STI approach for the VLSI technology, deep trenches are typically made in the substrate by reactive ion etching. The trenches are typically about 5-6 um. deep, about 2-3 um. wide and spaced about 2.5.-3.5 um. apart from another trench. The ULSI technology requires trenches that are deeper and spaced closer together posing new problems of field turn-on, punchthrough, gap-fill within the trenches and others. STI's can be made using, for instance, Buried Oxide (BOX) isolation for the shallow trenches. The method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO.sub.2) and then etching back or mechanically/chemically polishing the SiO.sub.2 to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the silicon substrate and are, for ULSI applications, typically between 0.5 and 0.8 micrometer (um.) deep. STI are formed around the active device to a depth between 4000 and 20000 Angstrom.
Following the forming of the trenches they are filled with a suitable dielectric material such as oxide, polysilicon or an organic polymeric material, for example polyimide. While the dielectric-filled trench isolation can provide effective dielectric isolation between devices, the fundamental disadvantage of this scheme is that the resulting structure tends to be non-planar. This lack of planarity is mainly due to the difference in the amount of fill that is required to fill a multiplicity of closely spaced trenches and the dielectric that is deposited on the surface of the substrate. This effect is further aggravated by the steps of bake and cure that are applied to the deposited dielectric in order to cure the dielectric and to evaporate the solvents from the dielectric. Further problems can be caused in this respect by the fact that in many chip designs there can be a significant difference in device density across the chip. In the design of memory chips for instance, the memory functions of the chip can consist of 10.000 or more memory elements. These memory elements are surrounded by their supporting logic functions which tend to have considerably lower density of active elements thereby further aggravating the problems of even distribution of the deposited dielectric across the surface of the chip and of obtaining good planarization for the entire surface of the chip. It is clear that poor planarity across the surface of the trenches leads to further problems in creating interconnect patterns and in depositing overlying layers of insulation and metalization. These overlying layers of metalization must be patterned and etched, a typically photolithographic process that requires constant and low depth of focus. Where this depth of focus is not as required, wire patterns of poor quality are created resulting a serious yield detractors and concerns of device reliability.
Another problem associated with the formation of STI regions is that if the silicon oxide is etched or polished to the surface of the silicon substrate, dishing occurs in the surface of the silicon oxide resulting in a concave surface of the STI regions. This results in recesses in the field oxide at the edge of the device areas. Later, when the gate electrodes are made for the FET's, the gate electrodes extend over the device area edge, causing an undesirable lower and variable threshold voltage when the devices are completed. It is therefore desirable to make isolation areas that extend higher than the substrate surface to avoid this problem while reducing manufacturing costs.
It must further be observed that recent requirements for the creation of holes within deep layers of either conducting or other materials have resulted in creating openings that have aspect ratios in excess of 3. It is beyond the capability of the existing techniques to fill gaps of this aspect ratio with High Density Plasma-oxide (HDP-oxide). This lack of adequate filling of gaps also occurs for holes that have a reentrant spacer profile. A reentrant spacer profile is a profile where the walls of the openings are not vertical but are sloped; this sloping of the walls makes complete penetration of the HPD-oxide into the hole difficult and, under certain conditions, incomplete.
As a consequence of incomplete deposition of HDP-oxide into high aspect ratio holes, keyholes or deposition irregularities will be formed. These keyholes or deposition irregularities are characterized by non-homogeneous deposition that form in the deposited HDP-oxide.
The indicated condition for the formation of a keyhole can also occur where a high aspect ratio through-hole is formed by RIE and where the formation position of the through-hole may deviate from the correct position due to mask misalignment or a process variation. The created through-hole can in this case exhibit a profile that inhibits complete and uniform deposition of HDP-oxide.
As an example of the formation of N-well and P-well structures, the formation of these structures for typical CMOS devices is highlighted below.
One of the advantages of the application of Complementary Metal Oxide Silicon (CMOS) devices is the reduced power consumption that can be achieved with these devices. This reduced power consumption is achieved by the fact that the CMOS devices use both N-channel and P-channel FET's whereby only one of the two transistors is on at any given time and virtually no current flows because of the high impedance of the device. The conventional CMOS devices are formed in and on single crystalline silicon semiconductor substrates by fabricating the N-channel FET's in P-wells in the silicon substrate while fabricating P-channel FET's in N-wells in the silicon substrate. The P-well is formed in the active device regions by ion implanting a P-type dopant such as boron (B.sup.11) in the P-well regions and an N-well dopant such as arsenic (Ar.sup.75) in the N-well regions. Conventional photolithographic techniques are used to form implant block-out masks to prevent implanting the P-type dopant in the N-well and the N-type dopant in the P-well. The substrate is then annealed to achieve the desired dopant profile, to activate the dopant and to remove dopant implant damage. Typically, the wells are between about 2.0 and 3.0 um deep and are doped to a concentration between about 1.0E15 and 1.0E17 atoms/cm.sup.3.
To form the source and drain regions for the CMOS devices, the p-well region is subjected to an n-type implant, for instance arsenic at a dose of between about 2.0E15 and 1.0E16 ions/cm.sup.2 and an energy of between about 20 and 70 KeV. The n-well region is subjected to a p-type implant, for instance boron at a dose of between about 1.0E15 and 1.0E16 ions/cm.sup.2 and an energy of between about 50 and 90 KeV.
In the formation of Shallow Trench Isolation regions for deep sub-micron processes, the silicon that surrounds the created trench for the STI region needs an ion field implantation. This implantation is required to prevent N.sup.+ to N-well and P.sup.+ to P-well punch-through. This field implant increases the junction capacitance of the STI region resulting in degraded device performance. The implant needs to penetrate the sides and the bottom of the STI trench, a deeper trench combined with the sub-micron dimensions of the trench surface results in very step sidewalls for the trench which limits the effectiveness of the required ion implant and, as a consequence, the effectiveness of preventing punchthrough of the STI region. The trench junction capacitance could be reduced by performing a deeper implant (higher implant energy); this approach is limited due to the trench angle for deep trench applications.
The invention addresses the problem of creating a STI region using a deep trench for sub-micron device feature size applications. The invention teaches a self-aligned process that does not require additional masking for creating a deep trench. The process of the invention results in a top trench with a relatively large angle of the sidewalls in addition to a bottom trench that provides the required isolation.
U.S. Pat. No. 5,721,174 (Peidous) discloses a (1) etch 1st Trench (2) form SiN spacer 60 in trench (3) etch 2nd trench 70, FIG. 4A (4) different (keep spacer) and (5) fill 1st and 2nd trench with oxide. This is close to the invention. Peidous does not remove the spacer in contrast with the invention's (4) that removes the spacer.
U.S. Pat. No. 5,854,121 (Gardner et al.) shows a STI process using spacers 20 and a one step trench etch.
U.S. Pat. No. 5,753,561 (Lee et al.) shows a method of etching STI trenches with rounded corners using a spacer.
U.S. Pat. No. 5,612,248 (Jeng) recites a STI process using a poly and an oxide spacer.
U.S. Pat. No. 5,372,968 (Lur et al.) teaches a STI method with a two step etch that uses SiN spacers. This differs from the invention.